Manufacturers of semiconductor devices routinely test their products at the wafer and packaged-device levels. The testing is usually carried out by a sophisticated system commonly referred to as automatic test equipment. The equipment generally drives waveforms to and detects outputs from one or more devices-under-test (DUT). The detected outputs are then compared to expected values to determine whether the device functioned properly.
A critical concern for semiconductor manufacturers is how to maximize use of the limited floor space available for test. Typically, stringent cleanliness requirements are imposed while testing semiconductor devices to minimize the possibility of failures due to dust or debris. To meet such requirements, the automatic test equipment resides in sophisticated clean rooms that minimize the size and number of particles according to particular applications. Because of the cost necessary to operate and maintain clean rooms, maximizing clean room floor space is essential to minimizing manufacturing costs.
One type of conventional semiconductor tester generally includes a mainframe computer, or test controller, and a testhead coupled to the controller via a relatively large cable bundle. The testhead typically weighs several hundred pounds and houses a plurality of channel cards that include complex circuitry for coupling to the semiconductor devices-under-test (DUTs). The testhead is fixed to a manipulator that moves and adjusts the testhead into a variety of positions as needed.
Efficient semiconductor device testing generally requires an apparatus to move and quickly connect the device-under-test (DUT) to the tester. To move wafers, a machine called a prober is employed. To manipulate packaged-parts, a device called a handler is used. These units precisely position the semiconductor devices so that they make contact with the outputs of the tester. Probers, handlers and other devices for positioning a DUT relative to the testhead are called generically "handling apparatus."
While the conventional tester described above appears beneficial for its intended applications, the necessity of a complex and automated manipulator to move and align the testhead in place adds undesirable expense to the tester system. Manipulators often cost upwards of a few hundred thousand dollars. Additionally, and even more importantly, the separate nature of the testhead combined with the floor space required for the manipulator adds up to a relatively large footprint. This undesirably reduces the number of testers capable of operating in a given clean room, reducing device throughput and increasing unit costs overall.
In an effort to address the tester footprint issue, one proposal for a semiconductor tester positions a mainframe/testbead unit vertically on top of a prober or handler. An example of this type of tester is found in the Teradyne Model J750 Tester, manufactured by Teradyne Inc., Boston, Mass. This construction dramatically reduces the tester footprint by making advantageous use of the vertical dimensions of the clean room. As a result, more testers are able to fit within a given horizontal clean room space.
Although the vertical configuration described above presents substantial footprint reduction benefits, the prober or handler generally supports the mainframe/testhead unit. As a result, a manipulator is still often required for servicing purposes, such as the initial installation of the unit or temporary removal of the mainframe/testhead unit from the handler or prober. Consequently, in order to plan for occasional servicing, space often must be made available in the clean room for the ingress and egress of the manipulator. The space set aside thus displaces potential floor room area for more testers and greater throughput.
What is needed and heretofore unavailable is a semiconductor test system that incorporates a minimal footprint and requires no manipulator for servicing. The integrated test cell of the present invention satisfies these needs.